سامانه همایش های دانشگاه آزاد اسلامی واحد نجف آباد

صفحه اصلی / International Conference on Artificial Intelligence; City, Industry and Health

پیاده سازی شتاب دهنده شبکه های عصبی کانولوشن بر روی FPGA

نویسندگان :

احسان قربانی¹ مهدی آمون²

1- Department of Electrical Engineering, Na.C., Islamic Azad University, Najafabad, Iran 2- Department of Electrical Engineering, Na.C., Islamic Azad University, Najafabad, Iran

کلمات کلیدی :

Implementation،Convolutional Neural Network،FPGA،Accelerator

چکیده :

In recent years, convolutional neural networks (CNNs) have appeared to be highly successful. As the convolutional neural networks are used for more complicated problems, their computational demands and storage space increase dramatically. In this view, the use of optimization techniques and specific hardware accelerators is vital in the improvement of their efficiency and performance. The aim of the present study is to implement a convolutional neural network accelerator for recognition and classification of handwritten digits of MINIST database on FPGA. The suggested convolutional network structure is first trained in MATLAB software. Subsequently, the hardware architecture of the network is implemented using high level synthesis (HLS) in Vivado software. Specifically, by offering a proper hardware pattern and acceleration using optimization techniques, the present study has improved operational parameters such as power, latency, and design area. The suggested architecture has been implemented in two 32-bit and 16-bit fixed point models. In the 16-bit model with accuracy recognition of 98.29% a proper reduction has obtained in the use of resources while observing the optimum and balanced consumption patterns in each of the existing resources in Zynq7z020 chip, hence allowing for setting it beside the other designed blocks as an IP core.